This invention relates to integrated circuit (IC) chip design, and particularly to implementation of engineering change orders (ECOs) to the design of IC chips.
Most digital integrated circuit (IC) chips are designed by a highly structured process based on a hardware description language (HDL) methodology. At a source design level, the circuit designer generates a source design document that describes the circuit to be incorporated into an IC chip. The IC design described in the source design is reduced to a design abstraction referred to as the registered transfer level (RTL), which is an IC design abstraction expressed in an HDL language such as Verilog or VHDL. The RTL design abstraction specifies the IC design by an RTL code that describes the operations of the IC chip that are performed on data as they flow between circuit inputs, outputs and clocked registers.
The IC design expressed by the RTL code is synthesized to generate a gate-level description, or netlist. Synthesis is the step taken to translate the architectural and functional descriptions represented by the RTL code to a lower level of representation of the design, such as logic-level and gate-level descriptions. The synthesis tool maps the RTL code into the netlist. Often, the synthesized design is resynthesized to optimize path delays, cell area, gate sizes and other features of the design. The result is often referred to as a resynthesized design.
Thereafter, the IC chip is constructed on a substrate containing a large number of cells that form circuit elements, such as transistors, capacitors, registers and other basic circuit elements. Each cell has one or more pins that are interconnected with complex connection patterns.
The source level document and RTL code are technologically independent. That is, the source level document and RTL code do not specify exact gates or logic devices to be implemented into the IC chip design. The gate-level description, or netlist, is technology dependent. This is because the synthesis tool uses a specific vendor""s technology library to map the technology-independent RTL code into the technology-dependent gate-level netlists.
At the RTL level, designers need to include all key design decisions, including design hierarchy and partitioning, clocking scheme, reset scheme and location of registers. Unexpected changes can negatively impact project schedules and cost.
During the design phase, it is often necessary to make local changes to the source design (that is, to the design described in the reference document from which the RTL code is generated). These local changes are usually described in an engineering change order (ECO). Usually, these ECOs are generated after the synthesis of the source design to the netlist is completed and the synthesized design is prepared.
In the past, the ECOs were performed simply by changing the source design and create an entirely new RTL code. The new RTL code was then resynthesized to create an entirely new netlist. While this technique was effective, it also required a considerable amount of time, and was expensive and wasteful because it required resynthesis of the entire RTL code, including portions not affected by the ECO. Accordingly, there is a need for a technique that implements ECOs without recreating an entirely new netlist.
The present invention is directed to a technique of direct transformation of ECO changes without additional general resynthesis of the source design.
In one form, at least one change is incorporated to cells of a synthesizable source design. A domain of the netlist is defined to contain cells that are equivalent to the cells of the source design that incorporate the change. The cells of the source design that incorporate the change are substituted for the domain in the netlist, and the substituted cells are resynthesized into the gate-level netlist.
In some embodiments, a domain is identified in the netlist that contains cells that are equivalent to cells in the source design. Synthesized design cells in the netlist are identified that are equivalent to source design cells in the source design. A border of the first domain is identified and synthesized design cells are identified that are equivalent to source design cells in at least the border.
In some embodiments, equivalency is based on flags associated with cells in both the design source and netlist. These flags are established in the design source and carried over to the netlist during a resynthesization process. Subsequent changes, such as due to an ECO, are addressed by finding equivalent cells in both the design source and the netlist, using the flags.
In one form, the invention is manifest in a computer readable program containing code that, when executed by a computer, causes the computer to perform the process steps to perform changes to the synthesized design of an IC design based on selected changes, such as ECOs. More particularly, a storage medium contains processor executable instructions that enable a processor to identify at least one domain of a gate-level netlist containing cells to be changed based on at least one change identified in a synthesizable source design. The domain containing cells that are equivalent to cells that are defined by the source design and that include the at least one change.